rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a cmos dual 8-bit buffered multiplying dac ad7628 functional block diagram general description the ad7628 is a monolithic dual 8-bit digital/analog converter featuring excellent dac-to-dac matching. it is available in small 0.3" wide 20-pin dips and in 20-terminal surface mount packages. separate on-chip latches are provided for each dac to allow easy microprocessor interface. data is transferred into either of the two dac data latches via a common 8-bit ttl/cmos compatible input port. control in- put dac a /dac b determines which dac is to be loaded. the ad7628s load cycle is similar to the write cycle of a ran- dom access memory, and the device is bus compatible with most 8-bit microprocessors, including 6502, 6809, 8085, z80. the device operates from a +12 v to +15 v power supply and is ttl-compatible over this range. power dissipation is a low 20 mw. both dacs offer excellent four quadrant multiplication charac- teristics with a separate reference input and feedback resistor for each dac. product highlights 1. dac to dac matching: since both of the ad7628 dacs are fabricated at the same time on the same chip, precise matching and tracking between dac a and dac b is inher- ent. the ad7628s matched cmos dacs make a whole new range of applications circuits possible, particularly in the audio, graphics and process control areas. 2. small package size: combining the inputs to the on-chip dac latches into a common data bus and adding a dac a / dac b select line has allowed the ad7628 to be packaged in a small 20-pin 0.3" wide dip, 20-pin soic, 20-terminal plcc and 20-terminal lcc. 3. ttl-compatibility: all digital inputs are ttl-compatible over a +12 v to +15 v power supply range. features on-chip latches for both dacs +12 v to +15 v operation dacs matched to 1% four quadrant multiplication ttl/cmos compatible from +12 v to +15 v latch free (protection schottkys not required) applications disk drives programmable filters x-y graphics gain/attenuation one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1996
t a = C40 8 ct a = C55 8 c parameter t a = +25 8 c 1 to +85 8 c to +125 8 c 1 units test conditions/comments static performance 2 resolution 8 8 8 bits relative accuracy 1/2 1/2 1/2 lsb max this is an endpoint linearity specification differential nonlinearity 1 1 l lsb max all grades guaranteed monotonic over full operating temperature range gain error 2 3 3 lsb max measured using internal rfb a and rfb b. both dac latches loaded with 11111111. gain error is adjustable using circuits of figures 4 and 5. gain temperature coefficient 3 d gain/ d temperature 0.0035 0.0035 %/ c max output leakage current out a (pin 2) 50 200 200 na max dac latches loaded with 00000000 out b (pin 20) 50 200 200 na max input resistance (v ref a, v ref b)88 8k w min input resistance tc = C300 ppm/ c, typical 15 15 15 k w max input resistance is 11 k w v ref a/v ref b input resistance match 1 1 1 % max digital inputs 4 input high voltage (v ih ) 2.4 2.4 2.4 v min input low voltage (v il ) 0.8 0.8 0.8 v max input current (i in ) 1 10 10 m a max v in = 0 or v dd input capacitance db0Cdb7 10 10 10 pf max wr , cs , daca /dacb 15 15 15 pf max switching characteristics 3 see timing diagram chip select to write set up time (t cs ) 160 160 210 ns min chip select to write hold time (t ch ) 10 10 10 ns min dac select to write set up time (t as ) 160 160 210 ns min dac select to write hold time (t ah ) 10 10 10 ns min data valid to write set up time (t ds ) 160 160 210 ns min data valid to write hold time (t dh ) 10 10 10 ns min write pulse width (t wr ) 150 170 210 ns min power supply see figure 3 i dd , k grade 2 2 ma all digital inputs v il or v ih b, t grades 2 2.5 2.5 ma all digital inputs v il or v ih all grades 100 500 500 m a all digital inputs 0 v or v dd specifications subject to change without notice. ac performance characteristics t a = C40 8 ct a = C55 8 c parameter t a = +25 8 c 1 to +85 8 c 1 to +125 8 p c 1 units test conditions/comments dc supply rejection ( d gain/ d v dd ) 0.01 0.02 0.02 % per % max d v dd = 5% current settling time 350 400 400 ns max to 1/2 lsb outa/outb load = 100 w . wr = cs = 0 v. db0Cdb7 = 0 v to v dd or v dd to 0 v digital-to-analog glitch impulse 330 nv sec typ for code transition 00000000 to 11111111 output capacitance c out a 25 25 25 pf max dac latches loaded with 00000000 c out b 25 25 25 pf max c out a 60 60 60 pf max dac latches loaded with 11111111 c out b 60 60 60 pf max ac feedthrough v ref a to out a C70 C65 C65 db max v ref a, v ref b = 20 v p-p sine wave v ref b to out b C70 C65 C65 db max @ 10 khz channel-to-channel isolation both dac latches loaded with 11111111. v ref a to out b C80 db typ v ref a = 20 v p-p sine wave @ 10 khz v ref b = 0 v see figure 6. v ref b to outa C80 db typ v ref b = 20 v p-p sine wave @ 10 khz v ref a = 0 v see figure 6. digital crosstalk 60 nv sec typ measured for code transition 00000000 to 11111111 harmonic distortion C85 db typ v in = 6 v rms @ 1 khz notes 1 temperature ranges are k version; C40 c to +85 c; b version; C40 c to +85 c; t version; C55 c to +125 c. 2 specification applies to both dacs in ad7628. 3 guaranteed by design but not production tested. 4 logic inputs are mos gates. typical input current (+25 c) is less than 1 na. specifications subject to change without notice. rev. a C2C ad7628Cspecifications (v dd = +10.8 v to +15.75 v, v ref a = v ref b = +10 v; out a = out b = 0 v unless otherwise noted) these characteristics are included for design guidance only and are not subject to test. v dd = +10.8 v to +15.75 v. (measured using recommended pc board layout (figure 7) and ad644 as output amplifiers)
ad7628 C3C rev. a absolute maximum ratings (t a = +25 c unless otherwise noted) v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v, +17 v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v, +17 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . v dd + 0.3 v dgnd to agnd . . . . . . . . . . . . . . . . . . . . . . . . v dd + 0.3 v digital input voltage to dgnd . . . . . . C0.3 v, v dd + 0.3 v v pin2 , v pin20 to agnd . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v v ref a, v ref b to agnd . . . . . . . . . . . . . . . . . . . . . . . 25 v v rfb a, v rfb b to agnd . . . . . . . . . . . . . . . . . . . . . . . 25 v power dissipation (any package) to +75 c . . . . . . . . 450 mw derates above +75 c by . . . . . . . . . . . . . . . . . . . 6 mw/ c operating temperature range commercial (k) grades . . . . . . . . . . . . . . . C40 c to +85 c industrial (b) grades . . . . . . . . . . . . . . . . . C40 c to +85 c extended (t) grades . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +300 c ordering guide temperature relative gain package model 1 range accuracy error option 2 ad7628kn C40 c to +85 c 1/2 lsb 2 lsb n-20 ad7628kp C40 c to +85 c 1/2 lsb 2 lsb p-20a ad7628kr C40 c to +85 c 1/2 lsb 2 lsb r-20 ad7628bq C40 c to +85 c 1/2 lsb 2 lsb q-20 ad7628tq C55 c to +125 c 1/2 lsb 2 lsb q-20 AD7628TE C55 c to +125 c 1/2 lsb 2 lsb e-20a notes 1 to order mil-std-883, class b process parts, add /883b to part number. contact your local sales office for military data sheet. 2 e = leadless ceramic chip carrier; n = plastic dip; p = plastic leaded chip carrier; q = cerdip; r = soic. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7628 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. terminology relative accuracy: relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after ad- justing for zero and full-scale, and is normally expressed in lsbs or as a percentage of full-scale reading. differential nonlinearity: differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb max over the operating temperature range ensures monotonicity. gain error: gain error is a measure of the output error between an ideal dac and the actual device output. it is measured with all 1s in the dac latches after offset error has been adjusted out. gain error of both dacs is adjustable to zero with exte rnal re sistance. output capacitance: capacitance from out a or out b to agnd. digital-to-analog glitch impulse: the amount of charge injected from the digital inputs to the analog output when the inputs change state. this is normally specified as the area of the glitch in either pa-secs or nv-secs, depending upon whether the glitch is measured as a current or voltage signal. glitch impulse is measured with v ref a, v ref b = agnd. channel-to-channel isolation: the proportion of input signal from one dacs reference input that appears at the output of the other dac, expressed as a ratio in db. digital crosstalk: the glitch energy transferred to the output of one converter due to a change in digital input code to the other converter. speci- fied in nv secs. pin configurations dip, soic agnd out a out b rfb b dgnd dac a/dac b (msb) db7 wr cs db0 (lsb) rfb a v ref a v ref b v dd db6 db1 db5 db2 db4 db3 1 2 20 19 5 6 7 16 15 14 3 4 18 17 813 912 10 11 top view (not to scale) ad7628 lccc v ref a dgnd db6 dac a /dac b db7 (msb) out a rfb b agnd out b db5 db4 db1 db3 db2 v ref b v dd db0 (lsb) wr cs 19 31 220 4 5 8 6 7 12 13 911 10 18 17 14 16 15 top view (not to scale) ad7628 rfb a plcc v ref a dgnd db6 dac a/dac b db7 (msb) rfb a out a rfb b agnd out b db5 db4 db1 db3 db2 v ref b v dd db0 (lsb) wr cs 19 3 1 2 20 4 5 8 6 7 12 13 9 11 10 18 17 14 16 15 top view (not to scale) ad7628
ad7628 C4C rev. a interface logic information dac selection both dac latches share a common 8-bit input port. the con- trol input dac a /dac b selects which dac can accept data from the input port. mode selection inputs cs and wr control the operating mode of the selected dac. see mode selection table below. write mode when c s and wr are both low, the selected dac is in the write mode. the input data latches of the selected dac are transpar- ent and its analog output responds to activity on db0Cdb7. hold mode the selected dac latch retains the data that was present on db0Cdb7 just prior to cs or wr assuming a high state. both analog outputs remain at the values corresponding to the data in their respective latches. mode selection table dac a / dac b cs wr dac a dac b l l l write hold h l l hold write x h x hold hold x x h hold hold l = low state, h = high state, x = dont care write cycle timing diagram circuit informationd/a section the ad7628 contains two identical 8-bit multiplying d/a con- verters, dac a and dac b. each dac consists of a highly stable thin film r-2r ladder and eight n-channel current steering switches. a simplified d/a circuit for dac a is shown in figure 1. an inverted r-2r ladder structure is used; that is, binary figure 1. simplified functional circuit for dac a weighted currents are switched between the dac output and agnd, thus maintaining fixed currents in each ladder leg inde- pendent of switch state. equivalent circuit analysis figure 2 shows an approximate equivalent circuit for one of the ad7628s d/a converters, in this case dac a. a similar equivalent circuit can be drawn for dac b. note that agnd (pin 1) is common for both dac a and dac b. the current source i leakage is composed of surface and junc- tion leakages and, as with most semiconductor devices, approxi- mately doubles every 10 c. the resistor ro, as shown in fig- ure 2, is the equivalent output resistance of the device, which varies with input code (excluding all 0s code) from 0.8r to 2r. r is typically 11 k w . c out is the capacitance due to the n-channel switches and varies from about 50 pf to 120 pf, depending on the digital input. g(v ref a, n) is the thevenin equivalent volt- age generator due to the reference input voltage v ref a and the transfer function of the r-2r ladder. for further information on cmos multiplying d/a converters, refer to cmos dac application guide, 2nd edition avail- able from analog devices, publication number g872aC15C4/86. figure 2. equivalent analog output circuit of dac a circuit informationCdigital section the input buffers are simple cmos level-shifters designed so that when the ad7628 is operated with v dd from 10.8 v to 15.75 v, the buffer converts ttl input levels (2.4 v and 0.8 v) into cmos logic levels. when v in is in the region of 1.0 volt to 2.0 volts, the input buffers operate in their linear region and pass a quiescent current (see f igure 3). to minimize power sup- ply currents, it is recommended that the digital input voltages be as close to the supply rails (v dd and dgnd) as practicably possible. the ad7628 may be operated with any supply voltage in the range 10.8 v dd 15.75 volts. figure 3. typical plot of supply current, i dd vs. logic input voltage v in to v dd = +15 v
ad7628 C5C rev. a table i. unipolar binary code table dac latch contents analog output msb lsb (dac a or dac b) 1 1 1 1 1 1 1 1 v in 255 256 ? ? ? ? 1 0 0 0 0 0 0 1 v in 129 256 ? ? ? ? 1 0 0 0 0 0 0 0 v in 128 256 ? ? ? ? = v in 2 0 1 1 1 1 1 1 1 v in 127 256 ? ? ? ? 0 0 0 0 0 0 0 1 v in 1 256 ? ? ? ? 0 0 0 0 0 0 0 0 v in 0 256 ? ? ? ? = 0 note: 1 lsb = (2 C8 )(v in ) = 1 256 v in () figure 4. dual dac unipolar binary operation (2 quadrant multiplication). see table i. figure 5. dual dac bipolar operation (4 quadrant multiplication). see table ii. table ii. bipolar (offset binary) code table dac latch contents analog output msb lsb (dac a or dac b) 1 1 1 1 1 1 1 1 + v in 127 128 ? ? ? ? 1 0 0 0 0 0 0 1 + v in 1 128 ? ? ? ? 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 v in 1 128 ? ? ? ? 0 0 0 0 0 0 0 1 v in 127 128 ? ? ? ? 0 0 0 0 0 0 0 0 v in 128 128 ? ? ? ? note: 1 lsb = (2 C7 )(v in ) = 1 128 v in () table iii. recommended trim resistor values trim resistor k/b/t r1; r3 500 r2; r4 150
ad7628 C6C rev. a applications information application hints to ensure system performance consistent with ad7628 specifi- cations, careful attention must be given to the following points: 1. general ground management: ac or transient voltages between the ad7628 agnd and dgnd can cause noise injection into the analog output. the simplest method of ensuring that voltages at agnd and dgnd are equal is to tie agnd and dgnd together at the ad7628. in more omplex systems where the agndCdgnd intertie is on the backplane, it is recommended that diodes be connected in inverse parallel between the ad7628 agnd and dgnd pins (1n914 or equivalent). 2. output amplifier offset: cmos dacs exhibit a code-dependent output resistance which, in turn, causes a code-dependent amplifier noise gain. the effect is a code- dependent diffe rential nonlinearity term at the amplifier output that depends on v os (v os is amplifier input offset voltage). this differential nonlinearity term adds to the r/2r differential nonlinear ity. to maintain monotonic operation, it is recommended that amplifier v os be no greater than 10% of 1 lsb over the temperature range of interest. 3. high frequency considerations: the output capacitance of a cmos dac works in conjunction with the amplifier feedback resistance to add a pole to the open loop response. this can cause ringing or oscillation. stability can be restored by adding a phase compensation cap acitor in parallel with the feedback resistor. dynamic performance the dynamic performance of the two dacs in the ad7628 will depend on the gain and phase characteristics of the output am- plifiers, together with the optimum choice of the pc board lay- out and decoupling components. figure 6 shows the relationship between input frequency and channel-to-channel isolation. figure 6. channel-to-channel isolation figure 7. suggested pc board layout for ad7628 with ad644 dual op amp figure 7 shows a printed circuit layout for the ad7628 and the ad644 dual op amp, which minimizes feedthrough and crosstalk. single supply applications the ad7628 dac r-2r ladder termination resistors are con- nected to agnd within the device. this arrangement is par- ticularly convenient for single supply operation because agnd may be biased at any voltage between dgnd and v dd . figure 8 shows a circuit that provides two +5 v to +8 v analog outputs by biasing agnd +5 v up from dgnd. the two dac refer- ence inputs are tied together and a reference input voltage is ob- tained without a buffer amplifier by making use of the constant and matched impedances of the dac a and dac b reference inputs. current flows through the two dac r-2r ladders into r1, and r1 is adjusted until the v ref a and v ref b inputs are at +2 v. the two analog output voltages range from +5 v to +8 v for dac codes 00000000 to l l l l l l l l . figure 8. ad7628 single supply operation figure 9 shows dac a of the ad7628 connected in a positive reference, voltage switching mode. this configuration is useful because v out is the same polarity as v in , allowing single supply operation. however, to retain specified linearity, v in must be in the range 0 v to +2.5 v and the output buffered or loaded with a high impedance (see figure 10). note that the input voltage is connected to the dac out a, and the output voltage is taken from the dac v ref a pin. figure 9. ad7628 single supply, voltage switching mode figure 10. typical ad7628 performance in single supply voltage switching mode
ad7628 C7C rev. a microprocessor interface figure 11. ad7628 dual dac to 6800 cpu interface programmable window comparator figure 13. digitally programmable window comparator (upper and lower limit detector) programmable state variable filter figure 12. ad7628 dual dac to 8085 cpu interface in the circuit of figure 13, the ad7628 is used to implement a programmable window comparator. dacs a and b are loaded with the required upper and lower voltage limits for the test, respectively. if the test input is not within the programmed lim- its, the pass/fail output will indicate a fail (logic zero). in this state, variable or universal filter configuration (figure 14) for dacs a1 and b1 control the gain and q of the filter characteristic, while dacs a2 and b2 control the cutoff fre- quency, f c . dacs a2 and b2 must track accurately for the simple expression for f c to hold. this is readily accomplished by the ad7628. op amps are 2 ad644. c3 compensates for the effects of op amp gain-bandwidth limitations. the filter provides low pass, high pass and band pass outputs and is ideally suited for applications where microprocessor con- trol of filter parameters is required, e.g., equalizer, tone con- trols, etc. programmable range for component values shown is f c = 0 khz to 15 khz and q = 0.3 to 4.5. figure 14. digitally controlled state variable filter circuit equations c 1 = c 2 , r 1 = r 2 , r 4 = r 5 f c = 1 2 p r 1 c 1 q = r 3 r 4 . r f r fbb 1 a o = C r f r s note dac equivalent resistance equals 256 dac ladder resistance () dac digital code
ad7628 C8C rev. a mechanical information outline dimensions dimensions shown in inches and (mm). c1029aC8C3/88 printed in u.s.a. digitally controlled dual telephone attenuator in this configuration, the ad7628 functions as a 2-channel digitally controlled attenuator; ideal for stereo audio and tele- phone signal level control applications. table iv gives input codes vs. attenuation for a 0 db to 15.5 db range. input code = 256 10 exp - attenuation, db 20 ? ? ? ? figure 15. digitally controlled dual telephone attenuator table iv. attenuation vs. dac a, dac b code for the circuit of figure 15 dac input code in dac input code in attn. db code decimal attn. db code decimal 0. 0 1 1 1 1 1 1 1 1 255 8.0 0 1 1 0 0 1 1 0 102 0.5 1 1 1 1 0 0 1 0 242 8.5 0 1 1 0 0 0 0 0 96 1.0 1 1 1 0 0 1 0 0 228 9.0 0 1 0 1 1 0 1 1 91 1.5 1 1 0 1 0 1 1 1 215 9.5 0 1 0 1 0 1 1 0 86 2.0 1 1 0 0 1 0 1 1 203 10.0 0 1 0 1 0 0 0 1 81 2.5 1 1 0 0 0 0 0 0 192 10.5 0 1 0 0 1 1 0 0 76 3.0 1 0 1 1 0 1 0 1 181 11.0 0 1 0 0 1 0 0 0 72 3.5 1 0 1 0 1 0 1 1 171 11.5 0 1 0 0 0 1 0 0 68 4.0 1 0 1 0 0 0 1 0 162 12.0 0 1 0 0 0 0 0 0 64 4.5 1 0 0 1 1 0 0 0 152 12.5 0 0 1 1 1 1 0 1 61 5.0 1 0 0 1 0 0 0 0 144 13.0 0 0 1 1 1 0 0 1 57 5.5 1 0 0 0 1 0 0 0 136 13.5 0 0 1 1 0 1 1 0 54 6.0 1 0 0 0 0 0 0 0 128 14.0 0 0 1 1 0 0 1 51 6.5 0 1 1 1 0 0 1 121 14.5 0 0 1 1 0 0 0 0 48 7.0 0 1 1 1 0 0 1 0 114 15.0 0 0 1 0 1 1 1 0 46 7.5 0 1 1 0 1 1 0 0 108 15.5 0 0 1 0 1 0 1 1 43 20-pin cerdip (q suffix) 20-pin plastic dip (n suffix) 20-terminal leadless chip carrier (e suffix) 20-terminal plastic leaded chip carrier (p suffix)
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